Comments

• I see. This becomes more clear, knowing the buffer holds the state of the filter. Thus, one buffer per signal.

  in filter phase delays / Fidlib, MNE-Python Comment by kevinjos March 2015
• Thanks all. This is a topic I am very interested in understanding better. It sounds to me like fidlib's high performance filters will be great for data visualization, in terms of zeroing the DC offset and perhaps eliminating the line noise. From an …

  in filter phase delays / Fidlib, MNE-Python Comment by kevinjos March 2015
• Thank you William. I am comparing the scipy filters that python-mne uses to the fidlib filters used by BrainBay. The FIR filters used by scipy/mne claim a zero-phase response. How do IIR bessel- or butterworth - type filters from fidlib work out in …

  in filter phase delays / Fidlib, MNE-Python Comment by kevinjos March 2015
• I am working on an open source, browser based, GUI for the OpenBCI. I tried to replicate the EKG experiment in the getting started section of the documentation without much success. The electrodes on my arm put out a signal centered around 30 mV and…

  in large millivolt data values / FbEEG Full Band EEG Comment by kevinjos March 2015
• Suppose an electrode is connected to N1P and N1P is connected to SRB2 which also has an electrode connected. What effect will the signal coming into N1N have on this circuit? Will the effect differ if N1N is connected or disconnected from SRB1 assum…

  in Differential Input Support? Comment by kevinjos March 2015
• Thanks biomurph. I only offered N1P against N2P as an example. It's good to know that differential input configuration only works within channel number (i.e. N1P against N1N). To further clarify, in order to use a differential input scheme, we must …

  in Differential Input Support? Comment by kevinjos March 2015
• Thanks for all the feedback. I went with a sync counter threshold in the state machine as flow control. We do not move data down stream until two sync'ed packets have been seen.

  in packets are 31 bytes over the air, then dongle adds header/footer Comment by kevinjos February 2015
• hmmmm, I implemented the state machine. Alls well on restart, the device returns to a happy state after the s, v, b sequence. However, on stop/start (s, b), I get some very interesting behavior. I see the sequence number consistently jump by 5. It's…

  in packets are 31 bytes over the air, then dongle adds header/footer Comment by kevinjos February 2015
• Thanks wjcroft. That's nice code, I will switch over my implementation.

  in packets are 31 bytes over the air, then dongle adds header/footer Comment by kevinjos February 2015
• Given this packet stream, where "s" is written to the uC while P3 is mid-assembly, should we expect a partial p3, no p3 or a full p3 to show up in the serial device? If partial or full, then before or after writing "b"?

  in packets are 31 bytes over the air, then dongle adds header/footer Comment by kevinjos February 2015
• I notice some sync issues after a stop and start or reset sequence (=>"s" =>"b" or =>"v" =>"b"). Specifically, after initiating the binary stream I see some header bytes that do not belong to the header of a packet. Thus far I have impl…

  in packets are 31 bytes over the air, then dongle adds header/footer Comment by kevinjos February 2015