understanding bias signal generation

chesswebchessweb
edited June 2015 in Cyton
In versions V1 and V2 the bias signal is generated basically just like it is recommended by Texas Instruments in the docs for the ADS1299 and the ADS1299 performance demo kit (see e.g. http://www.ti.com/lit/gpn/ads1299 Fig. 47 or http://www.ti.com/lit/pdf/slau443 Fig. 59).

That is there is an RC feedback circuit connecting BIAS_INV and BIAS_OUT, BIAS_OUT is connected to BIAS_IN, and finally BIAS_OUT is broken out to supply the bias signal via a dedicated electrode to the patient.

There are differences with respect to the TI docs, however: The TI docs use BIAS_INV (i.e. the *filtered* BIAS_OUT) to go to subsequent daisy chained ADS1299s, while the OpenBCI V1 and V2 boards use BIAS_OUT directly, thus *unfiltered*, for that purpose. How does this make sense?
Another difference is BIAS_REF. In V1 and V2 the potential on BIAS_REF is undefined since pin 60 is unconnected. According to the docs, BIAS_REF is the non-inverting input of an OpAmp, so how does it make sense to let it float?

On the V3 board schematics the deviations from the TI docs are even more significant. Here, there is no feedback connection between BIAS_OUT and BIAS_INV whatsoever. Instead, the *RC filtered* BIAS_OUT is broken out towards the bias electrode. BIAS_REF now is connected to AGND.

I can't find anything like the V3 approach in the TI docs. So why does it work at all and what were the reasons for the design deviations?

Comments

  • adminadmin
    The BIAS generation on the ADS1299 is not that complex, but can be complicated.
    You are right tha the BIAS_INV is used as an input from daisy-chained BIAS_OUT pins, to include as many BIAS signals as you like from stacked devices.
    The BIAS_REF is there if you want to insert your own reference to the internal circuitry (Op Amp), but we are using the internal BIAS generation by setting the appropriate bits in the CONFIG3 register. The BIAS_REF pin does not 'float'.
    Our 3V design made improvements to the V2 after lots of empirical testing with different configurations on the BIAS output. We found that the RC placement in V3 gave us the lowest noise result. 
    If you go to the TI forums, there is also lots of conversation about how the BIAS generation should be treated. There too, are some great arguments for the kind of design we're using.

  • che_guevarache_guevara
    Dear all,

    Looking at the schematic of the 32bit board, I see that the BIAS_OUT and the BIAS_IN signals are shorted together driving an RC circuit, whose output signal is named BIAS_DRV.

    I see that this signal is protected by the TPDE1806 ESD clamp, but then, is it biasing 8N/8P?

    If you're doing this, how are you routing the signals inside the chip? Are you having all the PGAs (except PGA8) generating the BIAS signal and you're shorting IN8N so that it gets this BIAS signal?

    Thanks for your help

    Best regards,

    Ernesto 
  • wjcroftwjcroft Mount Shasta, CA
    Ernesto, did you look at the other posts describing BIAS generation with the Search box at lower right? For example,


    William
  • wjcroftwjcroft Mount Shasta, CA
    edited June 2015
    Ernesto, I also merged your post into this existing thread on BIAS wiring. Also try this other search,

    http://openbci.com/forum/index.php?p=/search&Search=bias_out

  • biomurphbiomurph Brooklyn, NY
    Hi #che_guevara,


    The BIAS does not connect to 8N and 8P. BIAS is it's own separate channel.

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