latency estimate? (for lazy time alignment)
matt_higger
boston
Hi everyone,
Like others, I'm interested in time aligning my stimulus to the openbci datastream but I want to avoid analog hardware triggering (via a photo-sensor or otherwise) as I'm handing a system off to a clinical collaborator who needs a portable, user-friendly setup. (Moreover, my stimulus is audio)
What does a typical latency (time between collection @ cyton and timestamp @ usb for first data in each packet) look like for a python/brainflow cyton setup look like? If I always use the same laptop/settings etc, can I expect this latency to be consistent within a session? Across sessions?
If the latency is constant within/across sessions and bounded above by .1 seconds or so, could I just use the timestamps received* knowing that I may sacrifice as much as .1 seconds of the start of a trial? My application focuses on EMG, where reaction times typically eat up the first .1 seconds of a trial anyway (i.e. no signal of interest).
*I'll fit a line to the timestamps to smooth out the packet issue
Thanks!
-Matt
Comments
Matt, hi.
Actual latency will depend on a large number of factors, such as usb serial port latency, OS buffering delays, OS scheduling delays, other processes running and competing for CPU. The timestamps are assigned when packets reach the laptop, not when they are sampled at the Cyton.
You COULD run an experiment and determine typical latencies. Since this is an audio stimulus, I assume you run an audio cable from the 1.5mm audio jack to your subject headphones, or an external speaker. Using a Y-cable, you could split this audio, running one cable to the headphones, and the 2nd to a "voltage divider" network. This network would reduce the millivolts or volts level signal down to lower millivolts (less than 3.3V). This can then be connected (temporarily) to one of the 'Aux' pins on the Cyton. There it can be sampled when the Cyton Aux channels are in 'analog' mode. These Aux samples are collected at exactly the same time as the normal 8 channels. So show exact timing of the trigger signal.
http://www.ohmslawcalculator.com/voltage-divider-calculator
Regards, William
https://docs.openbci.com/docs/02Cyton/CytonExternal#programmatically-setting-board-mode
Thanks William. That idea got me dreaming a bit, I'd imagine I could use a microphone too for "wireless" syncing in a similar way.
I'm still interested in these questions though:
Is latency consistent throughout a session?
Is it feasible that ubuntu/python/cyton/brainflow configurations exceed a latency of .1 seconds? Has anyone built the analog splitter and measured latency explicitly?
Latency should be relatively consistent, assuming the areas I previously mentioned are not variable. Cyton transmits a packet every 4 ms, 250 Hz. Usb serial port buffering delays within a lightly loaded laptop, should be on the order of a few packets. Not 25 packets (.1 second at 250Hz.)
Note that Python is interpreted, and thus the interpreter (depending on JIT just-in-time compilation / caching, if supported), can introduce variable latency. As the JIT cache may vary in what it can hold.
https://www.google.com/search?q=does+python+use+jit
Other programming languages, such as C, C++, should be immune to JIT cache effects. But still impacted by processor load, scheduling delays, etc.
Your response raises one more question: if I'm using the brainflow API (written in C++, I think), I think I should be immune to the JIT cache effects, right?
Again, thanks for all the help William!
Depends on what Python you are using. Did you read the link I gave? The only real way to get an estimate is to try the test I suggested. Should be possible to setup in 10 minutes.